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Design of a programmable interrupt controller in VHDL: 4 steps



Programmable Interrupt Controller (PIC) receives multiple interrupts from external peripherals and merges them into a single interrupt output to a target processor core.

PIC is controlled by control and status register. All PIC registers are memory mapped and accessed via AHB3-Lite bus interface.

The registry bank consists of configuration registers, activation registers, pending registers, service registers, priority registers and ID registers, which are typical in Interrupt Controllers.

Configuration register is used to set the PIC operating mode. It can work in either fully nested mode or equally prioritized mode.

Each interrupt can be assigned priorities and masked individually. Global masking of all interruptions is also supported.

The Register Bank interacts with Priority Resolver and BTC (Binary-Tree-Comparator) to resolve the pending interrupt priorities and assert interruptions to the processor accordingly. ID registers contain ID for highest priority pending interruptions.


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